#include <at32f403a_407.h>
#include <string.h>

#include "bsp_board.h"
#include "bsp_lcd.h"

#include "lvgl.h"
#include "lv_port_disp.h"
#include "lv_port_tick.h"
#include "lv_demo_benchmark.h"

static void sclk_240m_hext_config(void)
{
    /* reset crm */
    crm_reset();
    crm_clock_source_enable(CRM_CLOCK_SOURCE_HEXT, TRUE);
    /* wait till hext is ready */
    while(crm_hext_stable_wait() == ERROR);
    /* config pll clock resource */
    crm_pll_config(CRM_PLL_SOURCE_HEXT_DIV, CRM_PLL_MULT_60, CRM_PLL_OUTPUT_RANGE_GT72MHZ); //8*60=480MHz
    /* config hext division */
    crm_hext_clock_div_set(CRM_HEXT_DIV_2); //480/2=240MHz
    /* enable pll */
    crm_clock_source_enable(CRM_CLOCK_SOURCE_PLL, TRUE);
    /* wait till pll is ready */
    while(crm_flag_get(CRM_PLL_STABLE_FLAG) != SET);
    /* config ahbclk */
    crm_ahb_div_set(CRM_AHB_DIV_1);
    /* config apb2clk */
    crm_apb2_div_set(CRM_APB2_DIV_2);
    /* config apb1clk */
    crm_apb1_div_set(CRM_APB1_DIV_2);
    /* enable auto step mode */
    crm_auto_step_mode_enable(TRUE);
    /* select pll as system clock source */
    crm_sysclk_switch(CRM_SCLK_PLL);
    /* wait till pll is used as system clock source */
    while(crm_sysclk_switch_status_get() != CRM_SCLK_PLL);
    /* disable auto step mode */
    crm_auto_step_mode_enable(FALSE);
    /* update system_core_clock global variable */
    system_core_clock_update();
    /* config systick delay */
    delay_init();
}

int main()
{
    nvic_priority_group_config(NVIC_PRIORITY_GROUP_4);
    sclk_240m_hext_config();
    uart_print_init(115200);
//    bsp_lcd_init();
    lv_init();
    lv_port_disp_init();
	delay_ms(500);
    lv_create_tick();
    lv_demo_benchmark();
    while(1) {
//		bsp_lcd_display_switch(1);
//		delay_ms(500);
//		bsp_lcd_display_switch(0);
//		delay_ms(500);
        lv_task_handler();
    }
}
